Iei-integration PCIE-Q350 v1.00 Manual de usuario Pagina 18
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Page xviii
PCIE-Q350 PICMG 1.3 CPU Card
Figure 7-65: IAMT Readme File............................................................................................... 205
Figure 7-66: IAMT Setup Operations ...................................................................................... 206
Figure 7-67: Completed Installation ....................................................................................... 206
- PCIE-Q350 PICMG 1.3 CPU Card 1
- Revision 2
- Manual Conventions 3
- Copyright 5
- Packing List 6
- Table of Contents 7
- List of Figures 14
- List of Tables 19
- BIOS Menus 21
- Glossary 22
- Introduction 23
- 1.1 Overview 24
- 1.2 PCIE-Q350 Overview 25
- 2 Detailed Specifications 31
- 2.1 Dimensions 32
- 2.2 Data Flow 33
- 2.3 Compatible Processors 34
- 1333 MHz 37
- An SDVO monitor 39
- DDC2B Compliant Interface 41
- 2.5 Intel 42
- ICH9DO Southbridge Chipset 42
- Page 24 46
- 2.7 PCI Bus Components 54
- 2.8 LPC Bus Components 56
- 2.8.3 Super I/O chipset 57
- 2.9 Ethernet LAN Controllers 59
- Page 38 60
- 2.11 Expansion Options 62
- 2.11.3 IEI Chassis 63
- Page 42 64
- Page 44 66
- 3 Unpacking 67
- 3.1 Anti-static Precautions 68
- 3.2 Unpacking 68
- 3.3 Unpacking Checklist 69
- 3.4 Optional Items 70
- Winbond TPM module 72
- (P/N: TPM-WI01-R10) 72
- 4 Connector Pinouts 73
- Page 54 76
- 4.2.1 ATX Power Connector 76
- Page 58 80
- PIN NO. DESCRIPTION 82
- 4.2.9 SATA Drive Connectors 89
- 9 Ground (GND) 10 N/C 92
- Page 72 94
- Page 74 96
- Page 78 100
- 5 Installation 101
- 5.1 Anti-static Precautions 102
- Read the user manual: 103
- Page 82 104
- 5.2.2 Installation Checklist 104
- 5.3 Unpacking 105
- Page 86 108
- Page 88 110
- WARNING: 110
- ONLY purchase DDR2 DIMM 112
- NOTE: 114
- 5.5.1 Clear CMOS Jumper 115
- Jumper Select Description 116
- 5.6 Chassis Installation 117
- 5.7.2 Audio Kit Installation 119
- Page 102 124
- 6 BIOS Screens 131
- 6.1 Introduction 132
- 6.2 Main 134
- 6.3 Advanced 135
- Page 115 137
- 6.3.2 IDE Configuration 137
- Primary IDE Master 139
- Primary IDE Slave 139
- Secondary IDE Master 139
- Secondary IDE Slave 139
- Page 118 140
- DEFAULT 146
- Page 127 149
- Page 128 150
- Page 129 151
- Page 132 154
- 6.3.5.2 AHCI Port n 154
- 6.4 PCI/PnP 165
- Page 144 166
- 6.5 Boot 168
- Page 147 169
- Page 151 173
- 6.5.3 Hard Disk Drives 173
- 6.6 Security 175
- 6.7 Chipset 176
- BIOS Menu 21: Chipset 177
- 6.8 Exit 182
- Page 161 183
- Page 162 184
- 7 Software Drivers 185
- 7.2 Driver CD Auto-run 186
- Page 165 187
- 7.3 Intel® Chipset Driver 188
- EXT to continue 190
- Page 170 192
- Page 172 194
- Page 173 195
- Page 174 196
- Page 175 197
- Figure 7-19 198
- Step 4: The window in 198
- Figure 7-20 appears 198
- Page 177 199
- NSTALL in Figure 7-27 203
- Page 182 204
- Figure 7-29 205
- Figure 7-30 appears 205
- Page 184 206
- EL during POST 213
- Page 192 214
- Page 193 215
- Page 194 216
- Page 195 217
- Page 196 218
- 7.8 Intel 219
- Page 198 220
- Step 5: 221
- Page 200 222
- Page 201 223
- Page 202 224
- Page 203 225
- A BIOS Options 229
- B DIO Interface 233
- B.2 DIO Connector Pinouts 234
- 17 GND N/A N/A 235
- 18 +5V N/A N/A 235
- Page 214 236
- C Watchdog Timer 237
- Page 218 240
- D Address Mapping 241
- D.1 Address Map 242
- D.3 IRQ Mapping Table 243
- D.4 DMA Channel Assignments 243
- Page 222 244
- E Intel 245
- Matrix Storage 245
- Manager 245
- E.1 Introduction 246
- E.2 Features and Benefits 247
- E.3 Accessing the Intel 247
- Matrix Storage Manager 247
- E.4 RAID Configuration 248
- Page 227 249
- NTER to 251
- NTER. See Figure E-8 253
- Page 232 254
- NTER. See Figure E-12 255
- Page 234 256
- Page 235 257
- Figure E-16: Exit Menu 258
- Figure E-17. Step 0: 258
- F Hazardous Materials 259
- Disclosure 259
- Page 238 260
- G Compatibility 263
- G.2 Compatible Processors 264
- Page 243 265
- G.4 Compatible CD ROM Drives 266
- H Index 267
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