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PCIE-Q350 PICMG 1.3 CPU Card
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6.3.3 Super IO Configuration
Use the Super IO Configuration menu (BIOS Menu 6) to set or change the
configurations for the FDD controllers, parallel ports and serial ports.
BIOS SETUP UTILITY
Main Advanced PCIPNP Boot Security Chipset Exit
Configure ITE8718 Super IO Chipset
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Serial Port1 Address [3F8/IRQ4]
Serial Port1 Mode [Normal]
Serial Port2 Address [2F8/IRQ3]
Serial Port2 Mode [Normal]
Allows BIOS to select
Serial Port Base
Addresses
Select Screen
↑ ↓ Select Item
Enter Go to SubScreen
F1 General Help
F10 Save and Exit
ESC Exit
v02.61 ©Copyright 1985-2006, American Megatrends, Inc.
BIOS Menu 6: Super IO Configuration
Serial Port1 Address [3F8/IRQ4]
Use the Serial Port1 Address option to select the Serial Port 1 base address.
Disabled
No base address is assigned to Serial Port 1
3F8/IRQ4 DEFAULT
Serial Port 1 I/O port address is 3F8 and the interrupt
address is IRQ4
3E8/IRQ4
Serial Port 1 I/O port address is 3E8 and the interrupt
address is IRQ4
2E8/IRQ3
Serial Port 1 I/O port address is 2E8 and the interrupt
address is IRQ3
- PCIE-Q350 1
- Revision 2
- Manual Conventions 3
- Copyright 5
- Packing List 6
- Table of Contents 7
- List of Figures 14
- List of Tables 19
- BIOS Menus 21
- Glossary 22
- Introduction 23
- 1.1 Overview 24
- 1.2 PCIE-Q350 Overview 25
- 2 Detailed Specifications 30
- 2.1 Dimensions 31
- 2.2 Data Flow 32
- 2.3 Compatible Processors 34
- 1333 MHz 37
- An SDVO monitor 39
- DDC2B Compliant Interface 41
- 2.5 Intel 42
- ICH9DO Southbridge Chipset 42
- Page 32 53
- 2.7 PCI Bus Components 54
- Page 34 55
- 2.8 LPC Bus Components 56
- Page 36 57
- 2.8.3 Super I/O chipset 57
- 2.9 Ethernet LAN Controllers 59
- 2.11 Expansion Options 62
- Page 42 63
- 2.11.3 IEI Chassis 63
- Page 44 65
- 3 Unpacking 66
- 3.1 Anti-static Precautions 67
- 3.2 Unpacking 67
- 3.3 Unpacking Checklist 68
- 3.4 Optional Items 69
- 4 Connector Pinouts 71
- Page 52 73
- 4.2.1 ATX Power Connector 74
- Page 54 75
- Page 56 77
- Page 58 79
- PIN NO. DESCRIPTION 80
- Page 60 81
- Page 62 83
- Page 64 85
- Page 66 87
- 4.2.9 SATA Drive Connectors 87
- 9 Ground (GND) 10 N/C 90
- Page 70 91
- Page 72 93
- 5 Installation 99
- 5.1 Anti-static Precautions 100
- Read the user manual: 101
- PCIE-Q350 PICMG 1.3 CPU Card 102
- 5.2.2 Installation Checklist 102
- 5.3 Unpacking 103
- WARNING: 108
- ONLY purchase DDR2 DIMM 110
- Page 90 111
- NOTE: 112
- Page 92 113
- 5.5.1 Clear CMOS Jumper 113
- Jumper Select Description 114
- 5.6 Chassis Installation 115
- Page 96 117
- 5.7.2 Audio Kit Installation 117
- Page 101 122
- 6 BIOS Screens 128
- 6.1 Introduction 129
- Page 110 131
- 6.3 Advanced 132
- Page 112 133
- 6.3.1 CPU Configuration 133
- Page 113 134
- 6.3.2 IDE Configuration 134
- Configuration 135
- Page 116 137
- DEFAULT 142
- Page 123 144
- Page 124 145
- Page 125 146
- Page 130 151
- 6.3.6.1 AHCI Port n 151
- 6.4 PCI/PnP 160
- 6.5 Boot 163
- 6.6 Security 167
- 6.7 Chipset 168
- 6.8 Exit 173
- Page 153 174
- 7 Software Drivers 175
- 7.2 Driver CD Auto-run 176
- Page 156 177
- 7.3 Intel® Chipset Driver 178
- EXT to continue 180
- Page 161 182
- Page 163 184
- Page 164 185
- Page 165 186
- Page 166 187
- Figure 7-19 188
- Step 20: The window in 188
- Figure 7-20 appears 188
- Page 168 189
- NSTALL in Figure 7-27 193
- Page 173 194
- Figure 7-29 195
- Step 4: The window in 195
- Figure 7-30 appears 195
- Page 175 196
- Step 0: 203
- Page 183 204
- Page 184 205
- Page 185 206
- Page 186 207
- Page 187 208
- 7.8 Intel 209
- Page 189 210
- Step 5: 211
- Page 191 212
- Page 192 213
- Page 193 214
- Page 194 215
- A BIOS Options 219
- B DIO Interface 223
- B.2 DIO Connector Pinouts 224
- 17 GND N/A N/A 225
- 18 +5V N/A N/A 225
- C Watchdog Timer 226
- D Intel 229
- Matrix Storage 229
- Manager 229
- D.1 Introduction 230
- D.2 Features and Benefits 231
- D.3 Accessing the Intel 231
- Matrix Storage Manager 231
- D.4 RAID Configuration 232
- Page 212 233
- NTER to 235
- Formatted: Bulle 236
- NTER. See Figure D-8 237
- NTER. See Figure D-12 239
- Page 219 240
- Figure D-16: Exit Menu 242
- Figure D-17. Step 0: 242
- E Hazardous Materials 243
- Disclosure 243
- Page 223 244
- F Compatibility 247
- F.2 Compatible Processors 248
- Page 228 249
- F.4 Compatible CD ROM Drives 250
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