Iei-integration SPXE-9S v1.00 Manual de usuario descargar pdf

SPXE-9S-R10

9-Slot PICMG 1.3 PCIe Backplane

User Manual Ver. 1.0

1. J1: PCI-X_A1 Frequency Setting

J2: PCI-X_B1 Frequency Setting

Freq. \ Pin 1 - 2 3 - 4

66MHz Don’t Care Short

100MHz Short Open

133MHz (Default) Open Open

2. J3 & J4: Intel Bridge 41210 SM-BUS Setting

Pin DESCRIPTION

1-2

Normal Operation

(default)

2-3

Test Purposes

3. J5: Intel Bridge 41210 Initialization Register Setting

J5 DESCRIPTION

Open (High) Initialization Register

Short (Low)

Normal response

(default)

4. J6: Intel Bridge 41210 Use MCU read/write Pin

Pin DESCRIPTION

1 MCLR

+5V

GND

RB7/PGD

RB6/PGC

Dec. 17, 2007

1 2 3 4 5

Indice de contenidos

Pagina 1 - SPXE-9S-R10

1SPXE-9S-R10 9-Slot PICMG 1.3 PCIe Backplane User Manual Ver. 1.0 1. J1: PCI-X_A1 Frequency Setting J2: PCI-X_B1 Frequency Setting Freq. \

Pagina 2

25. USB1, USB2: External 4 Port USB Connectors From the Mainboard 6. FAN1, FAN2, FAN3, FAN4: Fan Connector 7. ATXCTL1: Backplane to

Pagina 3 - 20 18 16 14 12 10

311. SM-BUS: External System Management BUS Connector 12.CN2: PCIE X8 SDVO Control Signal Pin The CN2 indicators are for controlling your PCI

Pagina 4

414. PCI routing table: 15. Notice: a. Recommend to use 6mm width spacer to install b. Torsion must less than 6lb-inch

Pagina 5 - 16. Dimension:

516. Dimension:

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