Iei-integration NANO-9452 v1.00 Manual de usuario Pagina 218
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Valorado. / 5. Basado en revisión del cliente
NANO-9452 EPIC Motherboard
Page 200
Step 8: Click NEXT and a warning appears (Figure 7-40). Read the warning carefully
and decide whether or not to continue the installation process.
Figure 7-40: Matrix Storage Manager Warning Screen
Step 9: Click N
EXT and a license agreement appears (Figure 7-41).
Figure 7-41: Matrix Storage Manager License Agreement
- Revision 2
- Copyright 3
- Packing List 4
- Table of Contents 5
- List of Figures 11
- List of Tables 14
- BIOS Menus 16
- Glossary 17
- Page xix 18
- 1 Introduction 19
- 1.1 Introduction 20
- 1.2 NANO-9452 Overview 21
- 2 Detailed Specifications 25
- 2.1 Overview 26
- 2.2 Dimensions 26
- 2.3 Data Flow 27
- 2.4 Compatible Processors 28
- 2.5 Intel 29
- 945GM Northbridge Chipset 29
- 2.7 PCIe Bus Components 35
- 2.8 LPC Bus Components 36
- 2.9.1 System Monitoring 39
- 3 Unpacking 41
- 3.1 Anti-static Precautions 42
- 3.2 Unpacking 42
- 3.3 Unpacking Checklist 43
- Page 26 44
- Page 28 46
- 4 Connector Pinouts 47
- Page 32 50
- Page 34 52
- PIN NO. DESCRIPTION 53
- 2 PS-ON 54
- 3 +5V Standby 54
- 4.2.5 Compact Flash Socket 55
- Page 38 56
- 1 GND 2 VCC 58
- 3 Output 3 4 Output 2 58
- 5 Output 1 6 Output 0 58
- 7 Input 3 8 Input 2 58
- 9 Input 1 10 Input 0 58
- 4.2.9 IDE Connector(44-pin) 61
- Page 44 62
- 3 IR-RX 63
- 5 IR-TX 63
- Page 50 68
- 19 GROUND 20 GROUND 69
- 21 GROUND 22 GROUND 69
- 23 GROUND 24 GROUND 69
- 25 GROUND 26 NC 69
- 30 -12V TBD2 TBD GND/3.3V 72
- 9 Ground (GND) 10 NC 75
- 1 GND 2 AGREEN_Y 76
- 3 GND 4 ARED_C 76
- 5 GND 6 ABLUE_CVBS 76
- 1 TXA+ 5 TXC 79
- 2 TXA- 9 TXB 79
- 3 TXB+ 10 TXD+ 79
- 4 TXC+ 11 TXD 79
- 1 DCD1 6 DSR1 80
- 2 RXD1 7 RTS1 80
- 3 TXD1 8 CTS1 80
- 4 DTR1 9 RI1 80
- 5 GROUND 10 80
- Page 64 82
- 5 Installation 83
- 5.1 Anti-static Precautions 84
- Read the user manual: 85
- Page 68 86
- 5.2.2 Installation Checklist 86
- NOTE: 95
- Short 1-2 Slave Default 96
- Short 2-3 Master 96
- 5.4.2 Clear CMOS Jumper 97
- Short 1-2 RS-232 Default 98
- Short 3-4 RS-422 98
- Short 5-6 RS-485 98
- Short 2-3 +5V LVDS 100
- NANO-9452 EPIC Motherboard 101
- 5.5 Chassis Installation 102
- Page 86 104
- 5.6.2 IDE Cable Connection 104
- Page 92 110
- 6 AMI BIOS 115
- 6.1 Introduction 116
- 6.2 Main 118
- 6.3 Advanced 119
- Page 103 121
- Primary IDE Master 123
- Primary IDE Slave 123
- Secondary IDE Master 123
- Secondary IDE Slave 123
- Page 106 124
- DEFAULT 130
- Page 118 136
- WARNING: 136
- Minimum Value: 0°C 137
- Maximum Value: 127°C 137
- Page 120 138
- PWM Minimum Mode: 0 139
- PWM Maximum Mode: 127 139
- 115200 8,n,1 DEFAULT 148
- 57600 8,n,1 148
- 38400 8,n,1 148
- 19200 8,n,1 148
- 09600 8,n,1 149
- 6.4 PCI/PnP 153
- 6.5 Boot 158
- Page 141 159
- CD/DVD 162
- Page 145 163
- Page 147 165
- 6.6 Security 166
- 6.7 Chipset 167
- Page 150 168
- Page 153 171
- Page 157 175
- Page 159 177
- Page 160 178
- 6.8 Exit 179
- Page 162 180
- Page 163 181
- Page 164 182
- 7 Driver Installation 183
- 7.2 Driver CD Auto-run 184
- Page 167 185
- Page 168 186
- Page 169 187
- Page 170 188
- Page 171 189
- Page 172 190
- Page 173 191
- Page 174 192
- Page 175 193
- Page 176 194
- Page 177 195
- Page 178 196
- Page 179 197
- Page 180 198
- Page 181 199
- Page 182 200
- Page 183 201
- Page 184 202
- EL during POST 203
- Page 187 205
- Page 188 206
- Page 190 208
- ” button. The install 210
- ” button 212
- (Figure 7-33) 213
- INISH” button. Step 0: 214
- Page 197 215
- Page 198 216
- Page 199 217
- Page 200 218
- Page 201 219
- Page 202 220
- A BIOS Options 221
- Page 208 226
- B DIO Interface 227
- B.2 DIO Connector Pinouts 228
- Page 212 230
- C Watchdog Timer 231
- Page 216 234
- D Address Mapping 235
- D.1 Address Map 236
- D.4 DMA Channel Assignments 237
- D.3 IRQ Mapping Table 237
- Page 220 238
- E Intel 239
- Matrix Storage 239
- Manager 239
- E.1 Introduction 240
- E.2 Features and Benefits 241
- E.3 Accessing the Intel 241
- Matrix Storage Manager 241
- E.4 RAID Configuration 242
- NTER. See Figure E-1 243
- NTER to 243
- NTER. See Figure E-8 247
- NTER. See Figure E-9 248
- NTER. See Figure E-12 250
- NTER. See Figure E-13 250
- F Index 253
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