Iei-integration NANO-9452 v4.02 Manual de usuario Pagina 119
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NANO-9452 EPIC Motherboard
Page 101
LBA Mode: Indicates whether the LBA (Logical Block Addressing) is a
method of addressing data on a disk drive is supported or not.
Block Mode: Block mode boosts IDE drive performance by increasing the
amount of data transferred. Only 512 bytes of data can be transferred per
interrupt if block mode is not used. Block mode allows transfers of up to 64 KB
per interrupt.
PIO Mode: Indicates the PIO mode of the installed device.
Async DMA: Indicates the highest Asynchronous DMA Mode that is
supported.
Ultra DMA: Indicates the highest Synchronous DMA Mode that is supported.
S.M.A.R.T.: Indicates whether or not the Self-Monitoring Analysis and
Reporting Technology protocol is supported.
32Bit Data Transfer: Enables 32-bit data transfer.
Type [Auto]
Use the Type BIOS option select the type of device the AMIBIOS attempts to boot from
after the Power-On Self-Test (POST) is complete.
Not Installed
BIOS is prevented from searching for an IDE disk
drive on the specified channel.
Auto DEFAULT
The BIOS auto detects the IDE disk drive type
attached to the specified channel. This setting should
be used if an IDE hard disk drive is attached to the
specified channel.
CD/DVD
The CD/DVD option specifies that an IDE CD-ROM
drive is attached to the specified IDE channel. The
BIOS does not attempt to search for other types of
IDE disk drives on the specified channel.
ARMD
This option specifies an ATAPI Removable Media
Device. These include, but are not limited to:
ZIP
LS-120
- NANO-9452 1
- Revision 2
- Copyright 3
- Manual Conventions 4
- Packing List 6
- Table of Contents 7
- List of Figures 13
- List of Tables 16
- BIOS Menus 18
- 1 Introduction 19
- 1.1 Introduction 20
- 1.2 NANO-9452 Overview 21
- Figure 1-2 22
- 2 Detailed Specifications 26
- 2.1 Overview 27
- 2.2 Dimensions 27
- 2.3 Data Flow 29
- 2.4 Compatible Processors 29
- Page 12 30
- 2.4.2 Supported Processors 30
- 2.5 Intel 31
- 945GME Northbridge Chipset 31
- 2.6 Intel 34
- ICH7M Southbridge Chipset 34
- 2.7 PCIe Bus Components 36
- 2.8 LPC Bus Components 37
- Page 22 40
- 2.9.1 System Monitoring 40
- 3 Unpacking 42
- 3.1 Anti-static Precautions 43
- 3.2 Unpacking 43
- 3.3 Unpacking Checklist 44
- Page 28 46
- 4 Connector Pinouts 47
- Page 32 50
- PIN NO. DESCRIPTION 51
- 2 PS-ON 51
- 3 +5V Standby 51
- 1 AC97_SYNC 2 AC97_BITCLK 52
- 3 AC97_SDOUT 4 AC97_PCBEEP 52
- 5 AC97_SDIN 6 AC97_RST# 52
- 7 AC97_VCC 8 AC97_GND 52
- 9 AC97_12V 52
- Page 36 54
- 4.2.4 CPU Power Connector 54
- 1 GND 2 VCC 56
- 3 Output 3 4 Output 2 56
- 5 Output 1 6 Output 0 56
- 7 Input 3 8 Input 2 56
- 9 Input 1 10 Input 0 56
- 1 Fan Speed Detect 57
- CN Label: 63
- Page 46 64
- Page 50 68
- 4.2.16 SATA Drive Connectors 68
- 7 GND 8 VCC 75
- PIN DESCRIPTION PIN 76
- DESCRIPTION 76
- 5 Installation 80
- 5.1 Anti-static Precautions 81
- 5.2.2 Installation Checklist 83
- Page 74 92
- 5.4.1 AT/ATX Power Select 92
- Open Slave Default 93
- Closed Master 93
- Page 76 94
- 5.4.3 Clear CMOS Jumper 94
- Short 1-2 RS-232 Default 95
- Short 3-4 RS-422 95
- Short 5-6 RS-485 95
- Short 2-3 +5V LVDS 96
- AT Power Select Description 97
- Short 1-2 5 V 97
- Short 2-3 3.3 V 97
- 5.5 Chassis Installation 98
- NANO-9452 EPIC Motherboard 103
- Page 90 108
- CAUTION: 108
- 6 BIOS Setup 109
- 6.1 Introduction 110
- 6.2 Main 112
- 6.3 Advanced 113
- Page 96 114
- 6.3.1 CPU Configuration 115
- Configuration 116
- Page 100 118
- DEFAULT 123
- Page 110 128
- Page 111 129
- 6.3.5 ACPI Configuration 129
- 6.4 PCI/PnP 142
- 6.5 Boot 148
- Page 134 152
- 6.5.3 Hard Disk Drives 152
- Page 135 153
- 6.6 Security 154
- 6.7 Chipset 155
- Page 140 158
- EFAULT 159
- Page 146 164
- Page 147 165
- Page 148 166
- 6.8 Exit 167
- Page 150 168
- 7 Driver Installation 169
- 7.2 Driver CD Auto-run 170
- ES to continue the setup 173
- 7.4 Intel 174
- Page 160 178
- EXT to continue 180
- EL during POST 182
- EXT. See Figure 7-25 183
- EXT” button. The install 186
- ES” button 187
- Page 171 189
- A BIOS Options 190
- B Terminology 195
- Page 178 196
- Page 179 197
- Page 180 198
- C Digital I/O Interface 199
- C.1 Introduction 200
- C.2 DIO Connector Pinouts 200
- D Watchdog Timer 202
- Page 185 203
- NOTE: 203
- E Address Mapping 205
- E.1 IO Address Map 206
- MB Memory Address Map 206
- E.3 IRQ Mapping Table 207
- E.4 DMA Channel Assignments 207
- F Compatibility 208
- F.2 Compatible Processors 209
- Page 192 210
- G Hazardous Materials 211
- Disclosure 211
- Mercury 212
- Page 195 213
- Page 196 214
- H AC'97 Audio Codec 215
- H.1 Introduction 216
- Page 201 219
- Page 202 220
- Page 203 221
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