Iei-integration NANO-9453 v1.10 Manual de usuario Pagina 72
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NANO-9453 EPIC Motherboard
Page 52
4.2.6 Digital Input/Output (DIO) Connector
CN Label:
DIO1
CN Type:
10-pin header (2x5)
CN Location:
See
Figure 4-8
CN Pinouts:
See
Table 4-8
The digital input/output connector is managed through a Super I/O chip. The DIO
connector pins are user programmable.
Figure 4-8: DIO Connector Locations
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 GND 2 VCC
3 Output 3 4 Output 2
5 Output 1 6 Output 0
7 Input 3 8 Input 2
9 Input 1 10 Input 0
Table 4-8: DIO Connector Pinouts
4.2.7 Fan Connector
CN Label:
CPU_FAN1
CN Type:
3-pin header
- NANO-9453 EPIC Motherboard 1
- Revision 2
- Copyright 3
- Manual Conventions 4
- Packing List 6
- Table of Contents 7
- List of Figures 13
- Page xvi 16
- List of Tables 17
- BIOS Menus 19
- Page xx 20
- 1 Introduction 21
- 1.1 Introduction 22
- 1.2 NANO-9453 Overview 23
- 2 Detailed Specifications 27
- 2.1 Overview 28
- 2.2 Dimensions 28
- 2.3 Data Flow 30
- 2.4 Compatible Processors 31
- Page 12 32
- 2.5 Intel 34
- 945GME Northbridge Chipset 34
- LVDS 35
- SDVO 35
- 32-bit downstream address 38
- 2.6 Intel 39
- ICH7-M Southbridge Chipset 39
- Supports two SATA drives 44
- 2.7 PCIe Bus Components 45
- JTAG support 46
- 2.8 LPC Bus Components 47
- AMI Flash BIOS 48
- Standard mode 50
- Enhanced mode 50
- High-speed mode 50
- Page 32 52
- Page 34 54
- 3 Unpacking 55
- 3.1 Anti-static Precautions 56
- 3.2 Unpacking 56
- 3.3 Unpacking Checklist 57
- Page 38 58
- Page 40 60
- 4 Connector Pinouts 61
- Page 44 64
- PIN NO. DESCRIPTION 66
- 2 PS_ON# 68
- 3 +5V Standby 68
- 1 AC97_SYNC 2 AC97_BITCLK 69
- 3 AC97_SDOUT 4 AC97_PCBEEP 69
- 5 AC97_SDIN 6 AC97_RST# 69
- 7 AC97_VCC 8 AC97_GND 69
- 9 AC97_12V 69
- Page 50 70
- 1 GND 2 VCC 72
- 3 Output 3 4 Output 2 72
- 5 Output 1 6 Output 0 72
- 7 Input 3 8 Input 2 72
- 9 Input 1 10 Input 0 72
- 4.2.9 IDE Connector(44-pin) 75
- Page 56 76
- 3 IR-RX 77
- 5 IR-TX 77
- Page 58 78
- 23 N/C 24 N/C 79
- 25 GROUND 26 GROUND 79
- 27 VCC_LVDS 28 VCC_LVDS 79
- 29 VCC_LVDS 30 VCC_LVDS 79
- Page 60 80
- 4.2.15 SATA Drive Connectors 85
- 1 TXD485# 87
- 2 TXD485+ 87
- 3 RXD485+ 87
- 4 RXD485# 87
- Page 68 88
- Page 70 90
- 1 MDIA3- 5 MDIA1+ 92
- 2 MDIA3+ 9 MDIA2+ 92
- 3 MDIA2- 10 MDIA0 92
- 4 MDIA1- 11 MDIA0+ 92
- 1 VCC 5 VCC 93
- 2 DATA- 6 DATA 93
- 3 DATA+ 7 DATA+ 93
- 4 GROUND 8 GROUND 93
- Figure 4-24: VGA Connector 94
- 5 Installation 95
- 5.1 Anti-static Precautions 96
- Read the user manual: 97
- Page 78 98
- 5.2.2 Installation Checklist 98
- 5.3.4 CF Card Installation 105
- NOTE: 107
- CF Card Setup Description 108
- Open Slave Default 108
- Short Master 108
- 5.4.2 Clear CMOS Jumper 109
- Short 5-6 RS-485 110
- Short 1-2 RS-232 Default 110
- Short 3-4 RS-422 110
- Short 2-3 +5V LVDS 111
- Short 1-2 VCC 112
- Short 2-3 VCC3 112
- 5.5 Chassis Installation 114
- USB cable 115
- RS-232/422/485 cable 115
- LPT cable 115
- ATX power cable 115
- Page 98 118
- Page 101 121
- Page 104 124
- Figure 5-25: USB Connector 129
- Page 110 130
- 6 AMI BIOS 131
- 6.1 Introduction 132
- 6.2 Main 134
- 6.3 Advanced 135
- Page 117 137
- Primary IDE Master 139
- Primary IDE Slave 139
- Secondary IDE Master 139
- Secondary IDE Slave 139
- Page 120 140
- DEFAULT 146
- CPU Temp. Limit of OFF 150
- Page 131 151
- Page 132 152
- Page 133 153
- Page 145 165
- 6.3.9 USB Configuration 165
- 6.4 PCI/PnP 169
- DM Channel 3 175
- DM Channel 5 175
- DM Channel 6 175
- DM Channel 7 175
- 6.5 Boot 176
- CD/DVD 179
- Page 160 180
- 6.6 Security 181
- 6.7 Chipset 182
- Page 165 185
- IGD DEFAULT 187
- PCI/IGD 187
- Page 169 189
- Page 170 190
- Page 171 191
- 6.8 Exit 192
- Page 173 193
- Page 174 194
- 7 Driver Installation 195
- 7.2 Driver CD Auto-run 196
- ES to continue the setup 198
- Page 181 201
- Page 182 202
- Page 183 203
- Page 184 204
- Page 185 205
- Page 186 206
- NEXT to 207
- EL during POST 207
- EXT. See Figure 7-24 209
- INISH” button. Step 0: 210
- EXT” button. The install 212
- ” button 213
- Page 195 215
- Page 196 216
- A BIOS Options 217
- Page 202 222
- B Terminology 223
- Page 204 224
- Page 205 225
- Page 206 226
- Page 207 227
- Page 208 228
- C DIO Interface 229
- C.2 DIO Connector Pinouts 230
- Page 212 232
- D Watchdog Timer 233
- Page 216 236
- E Address Mapping 237
- E.1 Address Map 238
- E.3 IRQ Mapping Table 239
- E.4 DMA Channel Assignments 240
- F Compatibility 241
- F.2 Compatible Processors 242
- Page 224 244
- G Hazardous Materials 245
- Disclosure 245
- Page 226 246
- H Index 249
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