Iei-integration PCIE-Q350 v1.30 Manual de usuario Pagina 202
- Pagina / 213
- Tabla de contenidos
- MARCADORES
- PCIE-Q350 1
- Revision 2
- Manual Conventions 3
- Copyright 5
- Packing List 6
- Table of Contents 7
- List of Figures 14
- List of Tables 18
- Page XIX 19
- BIOS Menus 20
- Introduction 21
- 1.1 Overview 22
- 1.2 PCIE-Q350 Overview 23
- 2 Detailed Specifications 28
- 2.1 Dimensions 29
- 2.2 Data Flow 30
- 2.3 Compatible Processors 32
- 440 1.86 GHz 533 MHz 1 MB 34
- 2.5 Intel 40
- ICH9DO Southbridge Chipset 40
- Page 28 48
- 2.7 PCI Bus Components 49
- 2.8 LPC Bus Components 50
- 2.10 Expansion Options 55
- Page 36 56
- 2.10.3 IEI Chassis 56
- Page 38 58
- 3 Unpacking 59
- 3.2 Unpacking 60
- 3.1 Anti-static Precautions 60
- 3.3 Unpacking Checklist 61
- 3.4 Optional Items 62
- 4 Connector Pinouts 64
- Page 46 66
- PIN NO. DESCRIPTION 67
- 1 SYNC 2 BITCLK 69
- 3 SDOUT 4 PCBEEP 69
- 5 SDIN 6 RST# 69
- 7 VCC 8 GND 69
- 9 +12V 10 N/C 69
- 2 +12VCC 71
- 3 Rotation Signal 71
- 4 Control 71
- 3 IR-RX 74
- 5 IR-TX 74
- 9 Ground (GND) 10 N/C 77
- 1 EXP_EN 79
- 2 SDVO_CLOCK 79
- 3 SDVO_DATA 79
- 1 VCC 2 GND 80
- 3 DATAN- 4 DATAM+ 80
- 5 DATAN+ 6 DATAM 80
- 7 GND 8 VCC 80
- 1 TXA+ 5 TXC 81
- 2 TXA- 6 TXB 81
- 3 TXB+ 7 TXD+ 81
- 4 TXC+ 8 TXD 81
- Figure 4-17: VGA Connector 83
- 5 Installation 84
- 5.1 Anti-static Precautions 85
- 5.2.2 Installation Checklist 87
- 5.3 Unpacking 88
- WARNING: 93
- Page 76 96
- Page 78 98
- 5.5.1 Clear CMOS Jumper 98
- 5.6 Chassis Installation 99
- NOTE: 100
- PCIE-Q350 PICMG 1.3 CPU Card 107
- Figure 5-19: VGA Connector 111
- 6 BIOS Screens 112
- 6.1 Introduction 113
- 6.3 Advanced 116
- 6.3.1 CPU Configuration 117
- Configuration 118
- Page 100 120
- DEFAULT 124
- Page 108 128
- Page 113 133
- 6.3.6.1 AHCI Port n 133
- 6.4 PCI/PnP 140
- 6.5 Boot 142
- Page 123 143
- 6.6 Security 145
- 6.7 Chipset 146
- 6.8 Exit 150
- Page 131 151
- 7 Software Drivers 152
- 7.2 Driver CD Auto-run 153
- Page 134 154
- 7.3 Intel® Chipset Driver 155
- EXT to continue 157
- Page 139 159
- Figure 7-12 160
- Page 141 161
- Page 142 162
- Page 143 163
- Page 145 165
- Step 0: 171
- Page 153 173
- Page 154 174
- Page 155 175
- Page 156 176
- 7.7 Intel 177
- Step 5: 178
- Page 159 179
- Page 160 180
- Page 161 181
- Page 162 182
- A BIOS Options 183
- B DIO Interface 186
- B.2 DIO Connector Pinouts 187
- 17 GND N/A N/A 188
- 18 +5V N/A N/A 188
- C Watchdog Timer 189
- Matrix Storage 192
- Manager 192
- D.1 Introduction 193
- D.2 Features and Benefits 194
- D.3 Accessing the Intel 194
- Matrix Storage Manager 194
- D.4 RAID Configuration 195
- Page 176 196
- NTER to 198
- NTER. See Figure D-8 200
- Page 181 201
- NTER. See Figure D-12 202
- Page 183 203
- Page 184 204
- Figure D-16: Exit Menu 205
- Figure D-17. Step 0: 205
- E Hazardous Materials 206
- Disclosure 206
- Mercury 207
- F Compatibility 210
- F.2 Compatible Processors 211
- Page 192 212
- F.4 Compatible CD ROM Drives 213
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