Iei-integration NANO-9453 v1.12 Manual de usuario Pagina 47
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NANO-9453 EPIC Motherboard
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SMIBIOS (DMI) compliant
Console redirection function support
PXE (Pre-boot Execution Environment) support
USB booting support
2.8.3 Super I/O chipset
The iTE IT8712F Super I/O chipset is connected to the ICH6 Southbridge through the LPC
bus. The iTE IT8712F is an LPC interface-based Super I/O device that comes with
Environment Controller integration. Some of the features of the iTE IT8712F chipset are
listed below:
LPC Interface
PC98/99/2001, ACPI and LANDesk Compliant
Enhanced Hardware Monitor
Fan Speed Controller
SmartGuardian Controller
Single +5V Power Supply
Two 16C550 UARTs for serial port control
One IEEE 1284 Parallel Port
Floppy Disk Controller
Keyboard Controller
Watchdog Timer
Serial IRQ Support
Vbat & Vcch Support
Single +5V Power Supply
Some of the Super I/O features are described in more detail below:
2.8.3.1 Super I/O LPC Interface
The LPC interface on the Super I/O complies with the Intel
®
Low Pin Count Specification
Rev. 1.0. The LPC interface supports both LDRQ# and SERIRQ protocols as well as PCI
PME# interfaces.
- NANO-9453 EPIC Motherboard 1
- Revision 2
- Copyright 3
- Manual Conventions 4
- Packing List 6
- Table of Contents 7
- List of Figures 13
- List of Tables 16
- BIOS Menus 18
- 1 Introduction 19
- 1.1 Introduction 20
- 1.2 NANO-9453 Overview 21
- 2 Detailed Specifications 25
- 2.1 Overview 26
- 2.2 Dimensions 26
- 2.3 Data Flow 28
- 2.4 Compatible Processors 29
- Page 12 30
- 2.5 Intel 32
- 945GME Northbridge Chipset 32
- LVDS 33
- SDVO 33
- 32-bit downstream address 36
- 2.6 Intel 37
- ICH7-M Southbridge Chipset 37
- Supports two SATA drives 42
- 2.7 PCIe Bus Components 43
- JTAG support 44
- 2.8 LPC Bus Components 45
- AMI Flash BIOS 46
- Standard mode 48
- Enhanced mode 48
- High-speed mode 48
- Page 32 50
- 3 Unpacking 52
- 3.1 Anti-static Precautions 53
- 3.2 Unpacking 53
- 3.3 Unpacking Checklist 54
- 4 Connector Pinouts 58
- Page 44 62
- PIN NO. DESCRIPTION 63
- 2 PS_ON# 65
- 3 +5V Standby 65
- Page 48 66
- 4.2.5 Compact Flash Socket 66
- Page 50 68
- 1 GND 2 VCC 69
- 3 Output 3 4 Output 2 69
- 5 Output 1 6 Output 0 69
- 7 Input 3 8 Input 2 69
- 9 Input 1 10 Input 0 69
- Page 52 70
- Page 54 72
- 4.2.9 IDE Connector(44-pin) 72
- 3 IR-RX 74
- 5 IR-TX 74
- 23 N/C 24 N/C 76
- 25 GROUND 26 GROUND 76
- 27 VCC_LVDS 28 VCC_LVDS 76
- 29 VCC_LVDS 30 VCC_LVDS 76
- Page 60 78
- Page 62 80
- Page 64 82
- 4.2.15 SATA Drive Connectors 82
- 1 TXD485# 84
- 2 TXD485+ 84
- 3 RXD485+ 84
- 4 RXD485# 84
- PIN DESCRIPTION PIN 89
- DESCRIPTION 89
- 1 VCC 5 VCC 90
- 2 DATA- 6 DATA 90
- 3 DATA+ 7 DATA+ 90
- 4 GROUND 8 GROUND 90
- Figure 4-24: VGA Connector 91
- 5 Installation 92
- 5.1 Anti-static Precautions 93
- Read the user manual: 94
- 5.2.2 Installation Checklist 95
- Page 80 98
- Page 82 100
- Page 84 102
- 5.3.4 CF Card Installation 102
- NOTE: 104
- CF Card Setup Description 105
- Open Slave Default 105
- Short Master 105
- 5.4.2 Clear CMOS Jumper 106
- Page 88 106
- Short 1-2 RS-232 Default 107
- Short 3-4 RS-422 107
- Short 5-6 RS-485 107
- Short 2-3 +5V LVDS 108
- Short 1-2 VCC 109
- Short 2-3 VCC3 109
- 5.5 Chassis Installation 110
- USB cable 111
- RS-232/422/485 cable 111
- LPT cable 111
- ATX power cable 111
- Page 96 114
- Page 102 120
- Figure 5-24: USB Connector 125
- 6 AMI BIOS 126
- 6.1 Introduction 127
- 6.2 Main 129
- 6.3 Advanced 130
- Page 114 132
- Configuration 133
- Primary IDE Master 134
- Primary IDE Slave 134
- Secondary IDE Master 134
- Secondary IDE Slave 134
- Page 117 135
- DEFAULT 141
- CPU Temp. Limit of OFF 145
- Page 128 146
- Page 129 147
- Page 130 148
- Page 142 160
- 6.3.9 USB Configuration 160
- 6.4 PCI/PnP 164
- Clear NVRAM [No] 165
- 6.5 Boot 171
- CD/DVD 174
- Page 157 175
- 6.6 Security 176
- 6.7 Chipset 177
- Page 162 180
- IGD DEFAULT 182
- PCI/IGD 182
- Page 166 184
- Page 167 185
- Page 168 186
- 6.8 Exit 187
- Page 170 188
- 7 Driver Installation 189
- 7.2 Driver CD Auto-run 190
- ES to continue the setup 192
- Page 177 195
- Page 178 196
- Page 179 197
- Page 180 198
- Page 181 199
- Page 182 200
- EL during POST 201
- EXT. See Figure 7-24 203
- INISH” button. Step 0: 204
- EXT” button. The install 206
- ” button 207
- Page 191 209
- A BIOS Options 210
- B Terminology 215
- Page 198 216
- Page 199 217
- Page 200 218
- Page 201 219
- C DIO Interface 220
- C.2 DIO Connector Pinouts 221
- D Watchdog Timer 223
- E Address Mapping 226
- E.1 Address Map 227
- E.3 IRQ Mapping Table 228
- E.4 DMA Channel Assignments 229
- F Compatibility 230
- F.2 Compatible Processors 231
- G Hazardous Materials 233
- Disclosure 233
- Page 216 234
- H Index 237
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